1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor memory and more specifically to a method for fabricating a semiconductor memory that can be utilized as a semiconductor non-volatile memory.
2. Description of Related Art
Recently, a semiconductor non-volatile memory is utilized as a memory of low-power consumption devices such as a cellular phone since it requires no electric power for retaining memory information.
As one of the semiconductor non-volatile memories a semiconductor non-volatile memory, in which a charge-storing layer is provided so as to sandwich a gate electrode, has been proposed (see Japanese Patent Application Laid-open (JP-A) No. 2006-24680 for example). Such semiconductor non-volatile memory functions as a memory by storing electrons in the charge storing layer. That is, it functions as a memory by changing a current value of a memory (transistor) depending on whether or not electrons exist in the charge storing layer and by reading the current value as data of “0” or “1”.
Meanwhile, refinement of elements used in the semiconductor memory is remarkable advanced lately and the same tendency is also seen in the field of semiconductor devices. For example, a fin-type field effect transistor has been proposed as a three-dimensional MIS type semiconductor memory (see JP-A No. 2002-118255 for example), which has a structure in which a sidewall insulating film is formed at a side surface of a convex thin film Si layer (fence) and a gate electrode.
However, it becomes difficult to implant impurities into a predetermined position during implanting of the impurities to source/drain regions formed on the fin, after the sidewall is formed on the fin (fence) of the fin-type field effect transistor. This is because a remaining sidewall becomes a mask for the implanting.
Still more, if a sidewall is not formed, a dimension of a gate is reduced and a width of the gate electrode becomes smaller according to the refinement of the semiconductor non-volatile memory having the charge storing layer. Then, a channel length of the memory becomes shorter to cause a short channel effect and a leakage current to flow between the source regions and the drain region even when the gate is closed (appropriately referred to as “punch-through” hereinafter).